Elastic membrane for semiconductor wafer polishing



FIG. 1 is a bottom perspective view of an elastic membrane for semiconductor wafer polishing showing our new design;

FIG. 2 is a top perspective view thereof;

FIG. 3 is a bottom view thereof;

FIG. 4 is a top view thereof;

FIG. 5 is a front view thereof, rear view being identical;

FIG. 6 is a right-side view thereof, left-side view being identical;

FIG. 7 is a cross-sectional view taken along line 7-7 of FIG. 4; and,

FIG. 8 is an enlarged portion view labeled FIG. 8 in FIG. 7.

The portions of the elastic membrane shown in even broken lines form no part of the claimed design. The dashed-dot lines in the drawings represent the boundary lines of the claimed design. The box labeled FIG. 8 shown in even broken lines in FIG. 7 defines the enlarged portion view of FIG. 8. 

CLAIM The ornamental design for an elastic membrane for semiconductor wafer polishing, as shown and described. 